Currently, the code isn’t pipelined and a future task is to add pipelining so that it computes a new pixel on each clock cycle, after some latency, of course. The repo contains the VHDL code and ...

After every clock cycle the simulator can decide whether the imulation continues with mode 1or with mode 2. Figure 2: Structural view for mode 1: Cosimulation Figure 3: A screenshot of the running ...