搜狐11 天
Verilog HDL数字集成电路设计原理与应用（第二版）蔡觉平课后习题 ...
《Verilog HDL数字集成电路设计原理与应用（第二版）》是大学电子工程、计算机工程等专业的重要教材之一。本书主要介绍了Verilog HDL语言的基础知识 ...
合见工软发布数字设计AI智能平台UDA，集成DeepSeek打造国产一站式智能 ...
中国数字EDA龙头企业上海合见工业软件集团有限公司（简称“合见工软”） 宣布推出创新的数字设计AI智能平台——UniVista Design Assistant ...
Hackaday6 年
Learn Verilog In Your Browser
The HDLBits site has a great set of Verilog “exams” that would be a big help to anyone trying to learn or brush up on their Verilog skills. The site offers a range of topics that go from the ...
无锡京师新专利发布，神经网络模型转换效率成倍提升
在当今科技迅猛发展的时代，各个领域都在不断探索和创新，尤其是一种新兴技术——神经网络，其应用正在逐渐改变我们的生活和工作模式。2025年2月12日，一则令人振奋的消息从金融界传来：无锡京师孵化管理有限公司近日向国家知识产权局申请了一项名为‘一种神经网络训练的模型向Verilog-A语言器件模型的转换方法’的专利，公开号CN119396409A，申请日期为2024年10月。这一专利的申请无疑是神经网 ...
Hackaday9 年
Learning Verilog For FPGAs: Hardware At Last!
In the previous pair of installments in this series, you built a simple Verilog demonstration consisting of an adder and a few flip flop-based circuits. The simulations work, so now it is time to ...
Design-Reuse4 年
System Verilog Assertions Simplified
Assertion is a very powerful feature of System Verilog HVL (Hardware Verification Language). Nowadays it is widely adopted and used in most of the design verification projects. This article explains ...
Design-Reuse5 年
System Verilog Macro: A Powerful Feature for Design Verification Projects
There are many other cases where we see code duplication. “System Verilog Macro” is one of the many solutions to address such duplication. Such macro is very efficient and can help save a lot of time ...