The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmission over controlled impedance transmission media such as copper cable ...
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY for PCIe 5.0 operates at 2.5Gbps, 5Gbps, 8Gbps, ...
2 and E1.L form factors starting early next year. However, the drive is limited to a PCIe Gen 4 interface with a 7GB/s read speed (1.005 million IOPs) and 3GB/s write speed while drawing 23W.