February 28, 2017 Matt Proud Comments Off on Taking a closer look at Rambus’ 56 Gbps multi-protocol SerDes PHY Rambus recently announced the launch of its 56G Multi-protocol SerDes (MPS) PHY developed ...
low latency Single & Quad-Lane PHY that supports USB protocol and its signalling needs. It has features like clocking and clock ... The Innosilicon 10G SERDES PHY is a highly configurable PHY capable ...
Moreover, a 112G XSR SerDes PHY should be designed with a system-oriented approach, maximizing flexibility for some of today’s most challenging applications including 112G die-to-die (D2D) interfaces, ...
Description: The Vortex Gearbox™ AVSP-1104 is a single-chip 100Gbps gearbox PHY IC designed for high-density 100G Ethernet and Optical Transport Networking (OTN) applications. The device supports full ...
Various digital control and tuning loops are ... The Innosilicon 25G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results
Feedback