Semiconductor Engineering1 天
Chiplets For Generative AI Workloads: Challenges in both HW and SW
A new technical paper titled “Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets” was published by researchers at University of Pittsburgh, Lightelligence, and ...
Semiconductor Engineering2 天
STCO for Dense Edge Architectures using 3D Integration and NVM (imec,, et al.)
Technology Co-Optimization for Dense Edge Architectures using 3D Integration and Non-Volatile Memory” was published by ...
Semiconductor Engineering3 天
Critical Design Considerations For High-Bandwidth Chiplet Interconnects (TSMC)
Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions” was ...
Semiconductor Engineering3 天
Pooling CPU Memory for LLM Inference With Lower Latency and Higher Throughput (UC Berkeley)
Pooling CPU Memory for LLM Inference” was published by researchers at UC Berkeley. Abstract “The rapid growth of LLMs has ...
Semiconductor Engineering3 天
Aging, Complexity, And AI In Analog Design
Where digital and analog designs are overlapping, and why it's becoming more difficult to ensure they work as expected over ...
Semiconductor Engineering3 天
Monitor Etch Defects on Dies in the Outer Regions Of The Wafer Using ISR
A technical paper titled “Detection of defective chips from nanostructures with a high-aspect ratio using hyperspectral ...
Semiconductor Engineering3 天
Gate-All-Around: TCAD and DTCO Approach To Evaluate Power and Performance (imec, et al.)
A new technical paper titled “Exploring GAA-Nanosheet, Forksheet and GAA-Forksheet Architectures: a TCAD-DTCO Study at 90 nm & 120 nm Cell Height” was published by imec, Huawei Technologies and Global ...
Semiconductor Engineering4 天
Outlook 2025: Embracing Chiplets
The semiconductor industry is rapidly evolving, and as we look towards 2025, chiplets are at the forefront of this transformation. The shift from traditional monolithic system-on-chip (SoC) designs to ...